1. Technical Field
The present disclosure relates to an optimized channel implant for a semiconductor device, such as a static random access memory (SRAM) device, and a method of forming same.
2. Discussion of the Related Art
In semiconductor devices, for example, SRAM devices, contact bridges may be formed between contacts in close proximity. Referring to FIG. 1, a plan view of a conventional semiconductor device 100 that can be disposed on an integrated circuit (IC) is shown. The device includes, for example, pass-gate (PG), pull-up (PU) and pull-down (PD) transistors. Using known lithography processes, a silicon substrate is etched to reduce the thickness of the silicon substrate, and form shallow trenches. Those portions of the silicon substrate that are not etched during lithography are referred to as silicon traces 102. A layer of polycrystalline silicon is applied on the silicon traces, and etched using known lithographic processes to form a plurality of polysilicon traces 104 on portions of the substrate including the silicon traces 102. FIG. 1 shows the configuration of the silicon and polysilicon traces 102, 104 with respect to each other. A single dielectric layer, or multiple dielectric layers, such as dielectric layers 110 and 112, are formed on the structure including the polysilicon traces 104. The dielectric layers 110 and 112 are etched to form cavities, such as cavity 113, shown in FIG. 2. Then, a conductive material such as, for example, tungsten, is deposited in the cavities to form conductive pillars. These pillars form conductive contacts or contact areas (CAs) 114, 116 that electrically contact the silicon and polysilicon traces 102, 104, respectively. The pillars also form contact area rectangle structures (CARECs) 118 to connect a gate (e.g., polysilicon trace 104) of one transistor to a source or drain of another transistor in close proximity.
FIG. 2 shows a cross sectional view of a portion the semiconductor device 100 shown in FIG. 1, as viewed along the B-cutting line in FIG. 1. As can be seen in FIG. 2, the CAREC 118 is formed in cavity 113 overlapping part of a polysilicon trace 104 and part of a silicon trace 102.
As is understood by those with ordinary skill the art, the polysilicon trace 104 is positioned over a channel area 120 of a transistor, and may serve as the gate of the transistor. On either side of the channel area 120 are source/drain regions 122 of the transistor that are oppositely doped with respect the channel region 120. For example, in the case of a p-channel field effect transistor (PFET), the source/drain regions are doped with P-type impurities and the channel region includes N-type doping, and in the case of an n-channel field effect transistor (NFET), the source/drain regions are doped with N-type impurities and the channel region includes P-type doping. For purposes of illustration, the drawings show a PFET, but it is to be understood that the illustrations of the conventional art, as well as of embodiments of the present inventive concept are merely examples, and are not so limited. Accordingly, it should be understood that the embodiments of the inventive concept also apply to NFET devices, wherein the dopants would be reversed from those in a PFET device.
With reference to FIG. 2, the source/drain regions 122 include a silicide layer 123 formed over a doped portion, in this case, a P-type doped portion. When the dielectric layers 110 and 112 are etched to form the cavity 113, part of the silicide layer 123 and part of the upper portion of the silicon trace 102 may be lost. As a result, when the cavity 113 is filled with conductive material to form the CAREC 118, the CAREC 118 extends below the top surface of the silicon trace 102 to electrically contact both the p-doped region and the n-doped region, thereby creating a short at area A1.
Accordingly, there exists a need for a semiconductor device, and method of forming a semiconductor device that avoids the n-p short created by leakage of the CAREC into the regions below the top surface of the silicon trace.